Cell Processing

Stable high voltages in solar cells and modules are becoming increasingly important as large PV systems are being set up in desert regions and are therefore exposed to high temperatures. High-voltage solar cells have lower temperature coefficients and thus produce a higher energy yield for such PV systems. Standard passivated emitter rear cell (PERC) devices have moderate voltages below 680mV, and also have the risk of degrading in such regions, because of light and elevated-temperature induced degradation (LeTID) effects and, in more recent observations, passivation degradation. This paper presents a solution for PERC producers to easily make the switch to n-type passivated emitter, rear totally diffused (nPERT) solar cells, which are capable of stable efficiencies above 22% and voltages close to 700mV, at almost no additional cost.

SolarWorld has played a pioneering role in triggering and implementing the shift from p-type multicrystalline aluminium backsurface field (Al-BSF) to p-type monocrystalline passivated emitter and rear cell (PERC) as the next mainstream solar cell technology, and recognized PERC to be the door opener to an extremely simple and cost-effective implementation of a bifacial solar cell. This paper reviews PERC technology development at SolarWorld, featuring an industrial baseline process for monocrystalline five-busbar (5BB) p-type PERC solar cells exceeding 22.0% median (22.5% maximum) cell efficiency by May 2018, before operations at SolarWorld came to a final halt.

Silicon heterojunction (SHJ) solar cells demonstrate a high conversion efficiency, reaching up to 25.1% using a simple and lean process flow for both-sides-contacted devices, and achieving a record silicon solar cell efficiency of 26.7% in back-contacted configuration. In addition, the field advantages of SHJ cell technology are a native bifaciality and low thermal coefficient providing impressive energy yield. Finally, the technology demonstrates potential cost reduction as it is perfectly suited for thin wafers integration. The SHJ technology is therefore today triggering strong interest in the PV industry, appearing on the roadmap of different cell manufacturers, with several production lines and pilot lines being installed worldwide. One limiting factor of the technology is related to the metallization: due to temperature restrictions on heterocontacts, the standard firing through silver paste needs to be replaced by low curing temperature paste. This type of pastes yield fingers with higher bulk resistivity (two to three times the one obtained with high temperature cured silver pastes) and lower adhesion after soldering. In this paper, materials, processes and costs figures will be reviewed for the metallization and module integration of SHJ solar cells, with a focus on copper plating benchmarked to silver screen-printing, for varying module interconnection technologies.

Improving PERC cells requires rather different strategies than standard cells have required, demanding concrete improvements in materials, manufacturing procedures and fabrication tools.

Improving the texturing approach for diamond wire-sawn (DWS) multicrystalline silicon (mc-Si) wafers is one of the key steps to decrease its efficiency gap with monocrystalline silicon-based solar cells. In this regard, black silicon texturing has increasingly caught attention of both academia and industries as a potential approach towards mass production of high-efficiency mc-Si solar cells. In this paper, the challenges of implementing such a texture, with unique feature sizes, in mass production are discussed in detail, and the latest results are reviewed. Finally, results of the first trials at high volume manufacturer applying an alternative plasma-less dry-chemical etching (ADE) method are presented.

State-of-the-art black-silicon texturing technology has been successfully implemented in all of the 4.5GW multi-Si cell production lines at Canadian Solar (CSI). With a combination of black-silicon texturing and diamondwire-sawn wafers, it has been possible to increase cell efficiency and wattage, while significantly reducing the cost. To further improve CSI’s multi-Si product performance and cost, multi-Si passivated emitter rear contact (multi-PERC) technology has been developed to achieve a mass production cell efficiency of more than 20% on average, and a module power exceeding 300W. By the end of 2017, a production capacity of over 1GW had been established, and CSI’s majority multi-Si cell capacity will be upgraded to PERC in 2018. This paper will introduce the solutions to realizing light-induced degradation (LID)-controlled multi-PERC cells and modules, as well as offering a discussion of the degradation performance. In addition, the technology evolution of CSI’s high-efficiency multi-Si products and a roadmap for 22%-efficiency multi-Si cells are presented.

TOPCon is regarded as a possible follow-up technology to the passivated emitter and rear cell (PERC) concept. This paper presents the latest results for high-efficiency solar cells, and the progress made on migrating layer deposition to high-throughput tools, which are already in use in industry. Possible metallization approaches, and three different industrially relevant solar cell structures featuring TOPCon, are also discussed.

We present an n-type bifacial IBC solar cell that uses a simple process comparable to our industrially proven n-type cell process for conventional H-grid front- and rear-contacted n-PERT cells. The process is based on tube diffusion and a simultaneous single-step screen-print of the contacts to both polarities, and has been demonstrated on an industrial line at pilot scale.

Relatively few experimental and academic studies about bifacial p-type PERC cells have been published to date. This paper looks at the experimental findings from JinkoSolar’s large area, industry-grade bifacial monocrystalline silicon PERC (biPERC) cells.

Because of its symmetrical a-Si/c-Si/a-Si structure, silicon heterojunction (SHJ) cell technology offers the possibility to use much thinner wafers, and thus to reduce material and production cost. In order to evaluate the industrial feasibility of these thinner heterojunction cells, wafers from the standard thickness of 160μm down to 40μm were processed on the heterojunction pilot line at CEA-INES.